1. Field of the Invention
The present invention relates to cache memory systems. More particularly, the present invention relates to non-inclusive hierarchical cache memory systems.
2. Background
Processors have achieved large gains in instruction processing bandwidth while the bandwidths of memory systems have not kept pace, resulting in a bandwidth mismatch between memories and processors. Memory bandwidth is the speed with which a memory device or system can transfer data from memory. Providing adequate memory bandwidth for a processor depends on the system architecture and the application requirements. One common solution for providing large memory bandwidths includes using a cache memory system that minimizes store or fetch latency ("memory latency") of instructions and/or data ("data") to or from main memory, respectively.
However, processors have continually increased in processing speed, increasing the need to provide even faster and more efficient cache memory systems so that such processors do not starve for want of data to process. Such a need for sufficient memory bandwidth is further exacerbated with computer systems having superscalar pipelined processors and/or processors that employ out-of-order processing which are commonly employed today. Superscalar processors have the ability to perform multiple instructions in parallel or in a single clock cycle, while out-of-order processors have the ability to execute instructions when their data is ready rather than in sequential order.
Accordingly, it would be desirable to provide an apparatus and method that optimizes a hierarchical cache memory system so that the amount of main memory fetches due to a cache miss are minimized.